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	<title><![CDATA[fpga Resources | ZDNet]]></title>
	<link><![CDATA[http://updates.zdnet.com/tags/fpga.html]]></link>
	<description><![CDATA[White papers, case studies, technical articles, and blog posts relating to fpga]]></description>
	<s:counts start="0" returned="20" found="45" />
	<language>en-us</language>
	<item>
		<title><![CDATA[Design Security in Stratix III Devices]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=1198697]]></link>
		<description><![CDATA[As FPGAs are increasingly used for critical system functions, protecting designs and Intellectual Property IP implemented inside FPGAs is becoming more important. Altera Stratix III devices are the first high-density and high-performance FPGAs to use the Advanced Encryption Standard AES with both non-volatile and volatile key programming to protect designs...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Tue, 01 Sep 2009 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/altera+corp..html"><![CDATA[Altera Corp.]]></category>
		<category domain="http://updates.zdnet.com/tags/stratix+corp..html"><![CDATA[Stratix Corp.]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/altera+stratix+iii+device.html"><![CDATA[Altera Stratix III Device]]></category>
		<category domain="http://updates.zdnet.com/tags/security.html"><![CDATA[Security]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ALTR</category>
		<category domain="tickers">ALTR</category>
	</item>
	<item>
		<title><![CDATA[BEE3: Revitalizing Computer Architecture Research]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=1140041]]></link>
		<description><![CDATA[In recent years, advances in computer architecture have slowed dramatically with most simulation results demonstrating only incremental architectural innovation. This is further exacerbated by increased processor and system complexity spurred by a seemingly unlimited number of transistors at computer architect's disposal. Computer architects produce a myopic view of their systems...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Wed, 06 May 2009 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/software.html"><![CDATA[Software]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/computer.html"><![CDATA[Computer]]></category>
		<category domain="http://updates.zdnet.com/tags/productivity.html"><![CDATA[Productivity]]></category>
		<category domain="http://updates.zdnet.com/tags/tools+%2526+techniques.html"><![CDATA[Tools & Techniques]]></category>
		<category domain="http://updates.zdnet.com/tags/management.html"><![CDATA[Management]]></category>
	</item>
	<item>
		<title><![CDATA[Power-Aware FPGA Design]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=971973]]></link>
		<description><![CDATA[Power consumption requirements in new, autonomous, multimedia-savvy consumer products that can store, transmit, and receive information have catapulted system architects and board and chip designers into a new realm. Even when designers attempted to reduce system power consumption, their approaches were not comprehensive and focused enough to achieve optimal results....]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Sun, 01 Feb 2009 00:00:00 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/technique.html"><![CDATA[Technique]]></category>
		<category domain="http://updates.zdnet.com/tags/actel.html"><![CDATA[Actel]]></category>
		<category domain="http://updates.zdnet.com/tags/aware.html"><![CDATA[Aware]]></category>
		<category domain="http://updates.zdnet.com/tags/board.html"><![CDATA[Board]]></category>
		<category domain="http://updates.zdnet.com/tags/power+consumption.html"><![CDATA[Power Consumption]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/productivity.html"><![CDATA[Productivity]]></category>
		<category domain="http://updates.zdnet.com/tags/corporate+governance.html"><![CDATA[Corporate Governance]]></category>
		<category domain="http://updates.zdnet.com/tags/business+operations.html"><![CDATA[Business Operations]]></category>
		<category domain="http://updates.zdnet.com/tags/corporate+law.html"><![CDATA[Corporate Law]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ACTL</category>
		<category domain="http://rss.financialcontent.com/stocksymbol">AWRE</category>
		<category domain="tickers">ACTL,AWRE</category>
	</item>
	<item>
		<title><![CDATA[Exploiting Reconfigurable Hardware for Network Security]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=1021945]]></link>
		<description><![CDATA[One type of network security strategy is using an Intrusion Detection System IDS. They are implementing IDS in FPGA-based Field Programmable Gate Array reconfigurable hardware. This is to achieve higher speed and more efficient performance of network security, as networks develop very fast with consequently more demanding constraints. This paper...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Thu, 01 Jan 2009 00:00:00 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/network.html"><![CDATA[Network]]></category>
		<category domain="http://updates.zdnet.com/tags/intrusion+detection+system.html"><![CDATA[Intrusion Detection System]]></category>
		<category domain="http://updates.zdnet.com/tags/hardware.html"><![CDATA[Hardware]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/university+of+oslo.html"><![CDATA[University Of Oslo]]></category>
		<category domain="http://updates.zdnet.com/tags/intrusion+detection.html"><![CDATA[Intrusion Detection]]></category>
		<category domain="http://updates.zdnet.com/tags/network+security.html"><![CDATA[Network Security]]></category>
		<category domain="http://updates.zdnet.com/tags/networking.html"><![CDATA[Networking]]></category>
		<category domain="http://updates.zdnet.com/tags/security.html"><![CDATA[Security]]></category>
	</item>
	<item>
		<title><![CDATA[High-Volume Nano FPGAs: Going Where No FPGA Has Gone Before]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=971983]]></link>
		<description><![CDATA[Electronic devices have found their way into every aspect of daily life. This popularity is driving demand for more portability and higher integration. While demand is increasing, design teams are challenged with meeting shorter time-to-market demands in their current design processes. Traditional ASIC and ASSP design technologies are limited by...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Sat, 01 Nov 2008 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/team.html"><![CDATA[Team]]></category>
		<category domain="http://updates.zdnet.com/tags/actel.html"><![CDATA[Actel]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/team+management.html"><![CDATA[Team Management]]></category>
		<category domain="http://updates.zdnet.com/tags/management.html"><![CDATA[Management]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ACTL</category>
		<category domain="tickers">ACTL</category>
	</item>
	<item>
		<title><![CDATA[Self-healing computers for NASA spacecraft]]></title>
		<link><![CDATA[http://blogs.zdnet.com/emergingtech/?p=903]]></link>
		<description><![CDATA[As you can guess, hardwired computer systems are much faster than general-purpose ones because they are designed to do a single task. But when they fail, they need to be totally reconfigured. This can be just a costly problem in a lab on Earth, but it can be vital in...]]></description>
		<s:doctype><![CDATA[Blog posts]]></s:doctype>
		<pubDate>Fri, 25 Apr 2008 10:18:58 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/nasa.html"><![CDATA[NASA]]></category>
		<category domain="http://updates.zdnet.com/tags/patent.html"><![CDATA[Patent]]></category>
		<category domain="http://updates.zdnet.com/tags/unit.html"><![CDATA[Unit]]></category>
		<category domain="http://updates.zdnet.com/tags/hardware.html"><![CDATA[Hardware]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/computer.html"><![CDATA[Computer]]></category>
		<category domain="http://updates.zdnet.com/tags/ua.html"><![CDATA[UA]]></category>
		<category domain="http://updates.zdnet.com/tags/ua+engineer.html"><![CDATA[UA Engineer]]></category>
		<category domain="http://updates.zdnet.com/tags/roland+piquepaille.html"><![CDATA[Roland Piquepaille]]></category>
	</item>
	<item>
		<title><![CDATA[Performance Analysis With High-Level Languages for High-Performance Reconfigurable Computing]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=391137]]></link>
		<description><![CDATA[High-Level Languages HLLs for FPGAs (Field-Programmable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher-level syntax, semantics, and abstractions, typically enabling faster development times than with traditional Hardware Description Languages HDLs. However, this abstraction is typically accompanied by some loss of performance as...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Tue, 18 Mar 2008 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/performance.html"><![CDATA[Performance]]></category>
		<category domain="http://updates.zdnet.com/tags/high-performance.html"><![CDATA[High-performance]]></category>
		<category domain="http://updates.zdnet.com/tags/computing.html"><![CDATA[Computing]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/performance+management.html"><![CDATA[Performance Management]]></category>
		<category domain="http://updates.zdnet.com/tags/human+resources.html"><![CDATA[Human Resources]]></category>
		<category domain="http://updates.zdnet.com/tags/workforce+management.html"><![CDATA[Workforce Management]]></category>
	</item>
	<item>
		<title><![CDATA[Black Hat, Day 1: Cracking GSM and skimming ATMs]]></title>
		<link><![CDATA[http://blogs.zdnet.com/security/?p=895]]></link>
		<description><![CDATA[Day 1 at Black Hat brought some outstanding talks.  The day started off with  David Hulton (aka h1kari, also the producer of ToorCon) and Steve from THC, who  presented on "Cracking GSM".  It was quite interesting due to the tie-in that  David has with Pico...]]></description>
		<s:doctype><![CDATA[Blog posts]]></s:doctype>
		<pubDate>Wed, 20 Feb 2008 17:40:55 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/black+hat.html"><![CDATA[Black Hat]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/gsm.html"><![CDATA[GSM]]></category>
		<category domain="http://updates.zdnet.com/tags/phishing.html"><![CDATA[Phishing]]></category>
		<category domain="http://updates.zdnet.com/tags/atm.html"><![CDATA[ATM]]></category>
		<category domain="http://updates.zdnet.com/tags/cyberthreats.html"><![CDATA[Cyberthreats]]></category>
		<category domain="http://updates.zdnet.com/tags/network+technology.html"><![CDATA[Network Technology]]></category>
		<category domain="http://updates.zdnet.com/tags/spam.html"><![CDATA[Spam]]></category>
		<category domain="http://updates.zdnet.com/tags/networking.html"><![CDATA[Networking]]></category>
		<category domain="http://updates.zdnet.com/tags/security.html"><![CDATA[Security]]></category>
		<category domain="http://updates.zdnet.com/tags/spam+and+phishing.html"><![CDATA[Spam And Phishing]]></category>
		<category domain="http://updates.zdnet.com/tags/nate+mcfeters.html"><![CDATA[Nate McFeters]]></category>
	</item>
	<item>
		<title><![CDATA[FPGA Design of Boyer-Moore Algorithm for Spyware Detection]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=390157]]></link>
		<description><![CDATA[Spyware is becoming increasingly destructive and sophisticated in threatening the privacy and efficient computing of the internet users. This new paradigm has opened the path for vendors to stop or substantially reduce the spreading of this uninvited program. Software and hardware approach has been identified to be implemented in order...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Mon, 11 Feb 2008 00:00:00 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/algorithm.html"><![CDATA[Algorithm]]></category>
		<category domain="http://updates.zdnet.com/tags/hardware.html"><![CDATA[Hardware]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/university+of+malaya.html"><![CDATA[University Of Malaya]]></category>
		<category domain="http://updates.zdnet.com/tags/spyware.html"><![CDATA[Spyware]]></category>
		<category domain="http://updates.zdnet.com/tags/spyware%252c+adware+%2526+malware.html"><![CDATA[Spyware, Adware & Malware]]></category>
		<category domain="http://updates.zdnet.com/tags/cyberthreats.html"><![CDATA[Cyberthreats]]></category>
		<category domain="http://updates.zdnet.com/tags/viruses+and+worms.html"><![CDATA[Viruses And Worms]]></category>
		<category domain="http://updates.zdnet.com/tags/security.html"><![CDATA[Security]]></category>
	</item>
	<item>
		<title><![CDATA[Light-Trail Testbed for Metro Optical Networks]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=376790]]></link>
		<description><![CDATA[Telecommunication networks have rapidly added staggering amounts of capacity to their long haul networks at low costs per bit using DWDM technologies. Concurrently, there has been a wave of new access technologies that are driving customers to demand high-speed, robust and customized data services. These dynamics have led to what...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Tue, 01 Jan 2008 00:00:00 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/iowa+state+university.html"><![CDATA[Iowa State University]]></category>
		<category domain="http://updates.zdnet.com/tags/optical+network.html"><![CDATA[Optical Network]]></category>
		<category domain="http://updates.zdnet.com/tags/network.html"><![CDATA[Network]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/streaming+media.html"><![CDATA[Streaming Media]]></category>
		<category domain="http://updates.zdnet.com/tags/web+site+development.html"><![CDATA[Web Site Development]]></category>
		<category domain="http://updates.zdnet.com/tags/web+technology.html"><![CDATA[Web Technology]]></category>
		<category domain="http://updates.zdnet.com/tags/optical+networking.html"><![CDATA[Optical Networking]]></category>
		<category domain="http://updates.zdnet.com/tags/fiber+optics.html"><![CDATA[Fiber Optics]]></category>
		<category domain="http://updates.zdnet.com/tags/digital+media.html"><![CDATA[Digital Media]]></category>
		<category domain="http://updates.zdnet.com/tags/networking.html"><![CDATA[Networking]]></category>
		<category domain="http://updates.zdnet.com/tags/internet.html"><![CDATA[Internet]]></category>
		<category domain="http://updates.zdnet.com/tags/telecommunications.html"><![CDATA[Telecommunications]]></category>
		<category domain="http://updates.zdnet.com/tags/consumer+electronics.html"><![CDATA[Consumer Electronics]]></category>
		<category domain="http://updates.zdnet.com/tags/personal+technology.html"><![CDATA[Personal Technology]]></category>
	</item>
	<item>
		<title><![CDATA[High Performance Computing by Context Switching Reconfigurable Logic]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=392676]]></link>
		<description><![CDATA[Reconfigurable computing has grown to become an important and large field of research. It is based on using Field Programmable Gate Arrays FPGAs. In this paper, this technology is introduced and it is shown how it can be applied for high speed computing. There is a large range of real-world...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Tue, 01 Jan 2008 00:00:00 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/high-performance+computing.html"><![CDATA[High-performance Computing]]></category>
		<category domain="http://updates.zdnet.com/tags/high-performance.html"><![CDATA[High-performance]]></category>
		<category domain="http://updates.zdnet.com/tags/computing.html"><![CDATA[Computing]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/university+of+oslo.html"><![CDATA[University Of Oslo]]></category>
	</item>
	<item>
		<title><![CDATA[Compiling PCRE to FPGA for Accelerating SNORT IDS]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=357337]]></link>
		<description><![CDATA[Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE Engine for regular expression matching on the payload. The software based PCRE Engine utilizes an NFA engine based on certain opcodes which...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Tue, 04 Dec 2007 00:00:00 -0800</pubDate>
		<category domain="http://updates.zdnet.com/tags/snort.html"><![CDATA[Snort]]></category>
		<category domain="http://updates.zdnet.com/tags/regular+expression.html"><![CDATA[Regular Expression]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
	</item>
	<item>
		<title><![CDATA[Driving with poor vision becomes possible]]></title>
		<link><![CDATA[http://blogs.zdnet.com/emergingtech/?p=720]]></link>
		<description><![CDATA[Spanish researchers have developed and successfully tested a computer simulator allowing visually impaired to drive. This system is called SERBA (short for 'Sistema Electro-Ã³ptico Reconfigurable de ayuda para Baja VisiÃ³n'), which means 'Reconfigurable Electric-Optical System for Low Vision' in English. This innovative system is based on a reconfigurable device known...]]></description>
		<s:doctype><![CDATA[Blog posts]]></s:doctype>
		<pubDate>Wed, 17 Oct 2007 09:19:24 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/patient.html"><![CDATA[Patient]]></category>
		<category domain="http://updates.zdnet.com/tags/vision.html"><![CDATA[Vision]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/strategy.html"><![CDATA[Strategy]]></category>
		<category domain="http://updates.zdnet.com/tags/management.html"><![CDATA[Management]]></category>
		<category domain="http://updates.zdnet.com/tags/roland+piquepaille.html"><![CDATA[Roland Piquepaille]]></category>
	</item>
	<item>
		<title><![CDATA[A Flexible Solution for Industrial Ethernet]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=374355]]></link>
		<description><![CDATA[This white paper describes the use of FPGA devices to deliver a multi-standard Industrial Ethernet capability from a single printed circuit board implementation. The benefits of FPGA implementation are described and an overview of the FPGA development flow, tools and technology used to create a universal but easy to maintain...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Mon, 01 Oct 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/ethernet.html"><![CDATA[Ethernet]]></category>
		<category domain="http://updates.zdnet.com/tags/altera+corp..html"><![CDATA[Altera Corp.]]></category>
		<category domain="http://updates.zdnet.com/tags/circuit+board.html"><![CDATA[Circuit Board]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ALTR</category>
		<category domain="tickers">ALTR</category>
	</item>
	<item>
		<title><![CDATA[Accelerating High-Performance Computing With FPGAs]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=391285]]></link>
		<description><![CDATA[The coprocessors from Xtreme Data and SRC represent the next step in HPC. The competitive advantages that application speed gives to users ensures that the demand for speed will continue to outpace what processors alone can achieve. Coprocessors based on Stratix III FPGAs provide the high-speed, low-latency interfaces that hardware...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Mon, 01 Oct 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/altera+corp..html"><![CDATA[Altera Corp.]]></category>
		<category domain="http://updates.zdnet.com/tags/high-performance+computing.html"><![CDATA[High-performance Computing]]></category>
		<category domain="http://updates.zdnet.com/tags/high-performance.html"><![CDATA[High-performance]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/business+structures.html"><![CDATA[Business Structures]]></category>
		<category domain="http://updates.zdnet.com/tags/leadership.html"><![CDATA[Leadership]]></category>
		<category domain="http://updates.zdnet.com/tags/productivity.html"><![CDATA[Productivity]]></category>
		<category domain="http://updates.zdnet.com/tags/finance.html"><![CDATA[Finance]]></category>
		<category domain="http://updates.zdnet.com/tags/management.html"><![CDATA[Management]]></category>
		<category domain="http://rss.financialcontent.com/stocksymbol">ALTR</category>
		<category domain="tickers">ALTR</category>
	</item>
	<item>
		<title><![CDATA[An FPGA Design Security Solution Using a Secure Memory Device]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=1198703]]></link>
		<description><![CDATA[FPGA designs are vulnerable to design theft because configuration bitstreams can be easily captured and copied. FPGAs are more vulnerable to cloning of the entire design rather than to Intellectual Property IP theft, since extracting IP from the bitstream is nearly impossible. In order to protect the configuration bitstream, some...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Mon, 01 Oct 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/security.html"><![CDATA[Security]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga+design.html"><![CDATA[FPGA Design]]></category>
	</item>
	<item>
		<title><![CDATA[A High Performance FPGA-Based Accelerator for BLAS Library Implementation]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=391101]]></link>
		<description><![CDATA[This paper describes the implementation and the performance analysis of a hardware accelerator for the BLAS library matrix multiplication operation. This accelerator is based on a dual-FPGA board and on an implementation BLAS software library making use of the FPGA-based hardware. In order to evaluate the performance of such a...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Fri, 29 Jun 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/accelerator.html"><![CDATA[Accelerator]]></category>
		<category domain="http://updates.zdnet.com/tags/high-performance.html"><![CDATA[High-performance]]></category>
		<category domain="http://updates.zdnet.com/tags/hardware.html"><![CDATA[Hardware]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/corporate+governance.html"><![CDATA[Corporate Governance]]></category>
		<category domain="http://updates.zdnet.com/tags/business+operations.html"><![CDATA[Business Operations]]></category>
		<category domain="http://updates.zdnet.com/tags/corporate+law.html"><![CDATA[Corporate Law]]></category>
	</item>
	<item>
		<title><![CDATA[Implementation of High Speed Streaming Video Data Transfer Application on FPGA]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=391270]]></link>
		<description><![CDATA[High speed streaming video data transfer operations are evolving with the onset of an era of high-end multimedia applications in compact digital devices. These data transfer applications become more crucial in high resolution video imaging. This paper talks about System-on-Chip architecture for storing and transferring high speed data from image...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Fri, 01 Jun 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/streaming+video.html"><![CDATA[Streaming Video]]></category>
		<category domain="http://updates.zdnet.com/tags/video.html"><![CDATA[Video]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/einfochips.html"><![CDATA[eInfochips]]></category>
		<category domain="http://updates.zdnet.com/tags/web+site+development.html"><![CDATA[Web Site Development]]></category>
		<category domain="http://updates.zdnet.com/tags/web+technology.html"><![CDATA[Web Technology]]></category>
		<category domain="http://updates.zdnet.com/tags/digital+video.html"><![CDATA[Digital Video]]></category>
		<category domain="http://updates.zdnet.com/tags/corporate+communications.html"><![CDATA[Corporate Communications]]></category>
		<category domain="http://updates.zdnet.com/tags/internet.html"><![CDATA[Internet]]></category>
		<category domain="http://updates.zdnet.com/tags/personal+technology.html"><![CDATA[Personal Technology]]></category>
		<category domain="http://updates.zdnet.com/tags/marketing.html"><![CDATA[Marketing]]></category>
	</item>
	<item>
		<title><![CDATA[A Programmable Parallel Processor Architecture in FPGAs for Image Processing Sensors]]></title>
		<link><![CDATA[http://whitepapers.zdnet.com/abstract.aspx?docid=396005]]></link>
		<description><![CDATA[In industrial image processing real-time requirements are very important issues. In future robot assistants, for example, object detection below 10 ms will be indispensable. This can only be met by over-sized DSP- /microcontroller working in a pixel serial manner with a high system clock. This paper presents a parallel processor...]]></description>
		<s:doctype><![CDATA[White papers]]></s:doctype>
		<pubDate>Fri, 01 Jun 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/sensor.html"><![CDATA[Sensor]]></category>
		<category domain="http://updates.zdnet.com/tags/image+processing.html"><![CDATA[Image Processing]]></category>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/robots.html"><![CDATA[Robots]]></category>
		<category domain="http://updates.zdnet.com/tags/processors.html"><![CDATA[Processors]]></category>
		<category domain="http://updates.zdnet.com/tags/emerging+technologies.html"><![CDATA[Emerging Technologies]]></category>
		<category domain="http://updates.zdnet.com/tags/semiconductors.html"><![CDATA[Semiconductors]]></category>
		<category domain="http://updates.zdnet.com/tags/hardware.html"><![CDATA[Hardware]]></category>
		<category domain="http://updates.zdnet.com/tags/components.html"><![CDATA[Components]]></category>
	</item>
	<item>
		<title><![CDATA[FIR HDL Writer 0.9.0 (Windows)]]></title>
		<link><![CDATA[http://downloads.zdnet.com/abstract.aspx?docid=558227]]></link>
		<description><![CDATA[FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA&apos;s or ASIC&apos;s. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates...]]></description>
		<s:doctype><![CDATA[Software downloads]]></s:doctype>
		<pubDate>Thu, 31 May 2007 00:00:00 -0700</pubDate>
		<category domain="http://updates.zdnet.com/tags/fpga.html"><![CDATA[FPGA]]></category>
		<category domain="http://updates.zdnet.com/tags/optunis.html"><![CDATA[Optunis]]></category>
		<category domain="http://updates.zdnet.com/tags/fir+hdl+writer.html"><![CDATA[FIR HDL Writer]]></category>
		<category domain="http://updates.zdnet.com/tags/asics.html"><![CDATA[ASICs]]></category>
		<category domain="http://updates.zdnet.com/tags/microsoft+windows.html"><![CDATA[Microsoft Windows]]></category>
		<category domain="http://updates.zdnet.com/tags/productivity.html"><![CDATA[Productivity]]></category>
		<category domain="http://updates.zdnet.com/tags/semiconductors.html"><![CDATA[Semiconductors]]></category>
		<category domain="http://updates.zdnet.com/tags/hardware.html"><![CDATA[Hardware]]></category>
		<category domain="http://updates.zdnet.com/tags/operating+systems.html"><![CDATA[Operating Systems]]></category>
		<category domain="http://updates.zdnet.com/tags/software.html"><![CDATA[Software]]></category>
	</item>
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