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- Continuous-Time Sigma-Delta ADC in 1.2-V 90-Nm CMOS With 61-DB Peak SNDR and 74-DB Dynamic Range in 10-MHz Bandwidth
- This paper describes a Continuous-Time Sigma-Delta CTSD analogue-to-digital converter ADC with 14-bit resolution, and a full-scale input 011.0 V p-p differential. The circuit is implemented in an 8-layer 90-nm 1.2-V CMOS process. Integrated into the macro is a low-jitter clock generator (LC-PLL). The macro is configurable to allow various oversampling...
- White papers 2008-07-01
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